The present invention relates to the field of data communications. More particularly, the invention relates to a method and apparatus for compensating the timing of data, received through a data-bus printed on a motherboard, that is sent from daughter-boards which are connected to the motherboard at different locations.
A data bus is widely used in computer and many data communications systems. A bus is usually implemented by disposing (e.g., printing) a group of data paths on a main printed circuit board called a xe2x80x9cmotherboardxe2x80x9d or a xe2x80x9cbackplanexe2x80x9d. Different functional modules that are required for the operation of the system are implemented on separate dedicated printed circuit board called xe2x80x9cdaughter-boardsxe2x80x9d. Each daughter-board is connected to the motherboard via a connector or a socket, which is located at different location. Data is transmitted to, and collected from each daughter-board via the bus by assigning time slots for each data source so that no more than one data source is transmitting at a time. The data is normally exchanged over the bus at a predetermined data-rate, which is controlled by a clocking circuit. In the operation of a bus which operates at very high speeds, the exact timing of the valid data is very important for their effective operation. For example, for a bus being operated at 100 MHz, a timing error of 10 nanoseconds will result in missing the valid data entirely, and errors less than 10 nanoseconds may also be problematic. At speeds of 100 MHz and above, the time for a signal to propagate along a trace path is not negligible, and must be taken into account.
In a high speed system such as an ATM (Asynchronous Transfer Mode) switch, information is broken up into small fixed cell sizes, which are transferred at high speed. The cells typically consist of 53 bytes or octets, which is composed of a 48 byte payload, and a 5 byte header. Different switches may add local switching information in the form of a header expansion. Each unit on a bus must be prepared to transfer its data, consisting of multiple data bits, when its turn on the bus is allocated. Due to the high speed nature of an ATM system, typically a synchronization signal is sent to the unit at least one clock period in advance, so that there will be no lost time between transmissions on the bus.
One prior art method for compensation of the delay uses a Phase-Locked-Loop (PLL) in each daughter-board to set the internal timing for that daughter-board. The internal timing clock signal of each individual daughter-board (i.e., the signal which determines the timing when data should be sent) is locked to the clock signal received over the mother board. Hence, a proper delay between the received main clock signal and the internal clock can be set individually for each daughter-board by varying the loop parameters until a desired phase-shift (i.e. the desired delay) is obtained. However, using a PLL in each card is cumbersome and costly.
Gunning-Transceiver-Logic (GTL) technology (by Texas Instruments Inc., USA) is a reduced voltage high speed interface standard that provides high-speed point to point data communication at a rate of 75-133 MHz, with a theoretical speed limit of 200 MHz. These data rates are achieved through low voltage swings, and carefully controlled termination that eliminates reflections. GTL technology is however expensive, and is limited to 200 MHz, as it does not compensate for inherent timing losses.
U.S. Pat. No. 4,744,076 discloses a system having a high-speed data communication bus disposed on a motherboard with associated modules that are connected to the motherboard by using removable connections. Modules communicate with the bus through transceiver arrays which are disposed on the motherboard as close as possible to the bus. This enables the removal or the location of modules without affecting the impedance and time delay characteristics of the bus. However, the delays are constant but are not equal for each module, and therefore data sent from each modules appears on the bus with a different timing delay, or phase relationship to the master clock.
U.S. Pat. No. 5,309,035 discloses an active delay regulator that precisely measures the propagation delay of a processed clock signal and maintains a fixed phase difference with relation to an input clock signal. The delay is measured by replicating the internal path delay (i.e., a xe2x80x9creplica loopxe2x80x9d) and passing the input clock signal through a selected tap of a tapped delay line. However, such active regulator (an integrated circuit) is required in each individual data source which feeds a bus, and hence, the system""s cost is increased.
All the methods described above have not yet provided satisfactory solutions to the problem of compensating for timing delays of data sent from daughter-boards which are connected to a motherboard at different locations, which is simple and cost effective.
It is an object of the present invention to provide a method and apparatus for compensating the timing of data sent from daughter-boards which are connected to a motherboard at different locations, to essentially equalize the timing, using no additional active component in each daughter-board.
It is another object of the present invention to provide a method and apparatus for compensating the timing of data sent from daughter-boards which are connected to a motherboard at different locations, to essentially equalize the timing, without using phase-locking techniques in each daughter-board.
Other objects and advantages of the invention will become apparent as the description proceeds.
The present invention is directed to a method for determining the timing of data arriving to a predetermined point via a data-bus from two or more data sources located at different locations along the data-bus. The timing initiated by a first clock signal, is selected from a plurality of clock signals at a frequency f, which are transmitted from a first clock generator. The total phase-shift of the data, relative to the phase of the transmitted first clock signal, is equalized for each data source. The total phase-shift is determined by transmitting a first clock signal via a separate transmission path and receiving it at the end of the path. The determined total phase-shift is then utilized for enabling the reading of the data. Equalization is carried out by generating, for each data source, a first transmission path for receiving the first clock signal and a second transmission path for transmitting data, so that the length of the sum of the first and the second transmission paths is substantially equal for each of the data sources.
Preferably, a data receiving point is determined and a plurality of data transmission paths from the receiving point to each source, forming the data-bus, is generated, where each data transmission path has a specific length. A clock signal transmission path with a unique length, is generated for each source, thereby generating a unique phase shift. The unique length of each of the clock signal transmission paths is substantially equal to the difference between a prefixed length and the specific length of the data transmission path of the each source. The first clock signal is transmitted to the source, and a first clock signal is transmitted via a dummy transmission path of a length which is substantially equal to the prefixed length, thereby shifting the phase of the second clock signal. A second clock generator, which may be part of a phase locked loop, is locked to the phase-shifted second clock signal, and the output of the locked clock generator is used to determine the timing for reading data arriving to the receiving point via the data-bus. Alternatively, a second clock signal at a frequency f/n (n=2, 3, . . . ) is transmitted via the dummy transmission path, so as to shift the phase of the second clock signal. Preferably, the data sources are circuits implemented on printed circuit boards, connected to a main printed circuit board. The transmission paths are traces printed on a printed circuit board.
Optionally, a synchronization pulse is transmitted, prior to data transmission, over a separate transmission path to one of the two or more data sources. The unique length of the synchronization pulse transmission path is substantially equal to the difference between a prefixed length and the specific length of the data transmission path of the source;
The present invention is also directed to a circuitry for determining the timing of data arriving to a predetermined point via a data-bus from two or more data sources located at different locations along the data-bus. The circuit comprises a plurality of data transmission paths, forming the data-bus, from each source to the receiving point, wherein each path has a specific length; a plurality of first clock signal transmission paths, each of which having a unique length being substantially equal to the difference between a prefixed length and the specific length of the data transmission path of the each source; a dummy transmission path having a length which is substantially equal to the prefixed length, and connected to the first clock signal; circuitry for transmitting the first clock signal to each source; circuitry for transmitting data via the data-bus, from each source to the receiving point at a timing being initiated by the first clock signal; and circuitry for reading in the data at the receiving point in response to the timing received over the dummy transmission path.
Preferably, the circuit further comprises circuitry for transmitting a synchronization pulse to each data source, and a transmission path for transmitting the synchronization pulse. The transmission path has a unique length which is substantially equal to the difference between a prefixed length and the specific length of the data transmission path of the each data source.
The present invention is also directed to a data communication system that comprises:
a) a motherboard;
b) one or more daughter-boards which are connected to said motherboard at different locations;
c) a data-bus printed on said motherboard, for receiving data that is sent from said one or more daughter-boards to said motherboard; and
d) circuitry for compensating the timing of said sent data by determining the timing of data arriving to a predetermined point via said data-bus from two or more data sources, located at different locations along said data-bus, to which said one or more daughter-boards are connected.
Preferably, the circuitry for compensating the timing of said sent data comprises:
a) a first clock signal at a frequency f, transmitted from a first clock generator;
b) a plurality of data transmission paths from each source to a receiving point, each of which having a specific length, said plurality of data transmission paths forming said data-bus;
c) a plurality of first clock signal transmission paths, each of which having a unique length being substantially equal to the difference between a prefixed length and the specific length of the data transmission path of said each source;
d) a dummy transmission path having a length being substantially equal to said prefixed length and being connected to said first clock signal;
e) circuitry for transmitting said first clock signal to each source;
f) circuitry for transmitting data via said data-bus, from each source to said receiving point at a timing being initiated by said first clock signal; and
g) circuitry for reading in said data at said receiving point in response to the timing received over said dummy transmission path.